Intel Xe-HPC die pictured
Intel’s SVP, Chief Architecture, GM of Architecture, Graphics and Software, Raja Koduri published the first picture of the multi-chip Xe-HPC GPGPU.
We get a first look at Intel Xe-HPC, an upcoming compute accelerator based on Intel Xe architecture. Intel has been teasing and talking about the HPC architecture for a while now. It was first revealed as Ponte Vecchio GPU back in 2019.
Last year Intel confirmed that Xe-HPC will be based on Foveros CO-EMIB packaging technology, as the processor itself will feature multiple chips manufactured using different fabrication nodes.
The base tile is manufactured using Intel’s 10nm SuperFin architecture, but for instance, the Rambo Cache Tile is already using 10nm Enhanced SuperFin architecture. The compute tile is made using Next-Gen & External nodes, while the Xe I/O Tile is manufactured using external foundry exclusively. In total there are 7 advanced silicon technologies, Raja Koduri claims on Twitter.
While the picture is not described, it appears that Xe-HPC GPU features 8 compute cores on two tiles, however, it is currently unknown how many Execution Units each tile holds. We can also see four HBM stacks for each of the two dies.
Today Raja Koduri confirmed that Xe-HPC is ready for power on, which means that the chip has been enabled at Intel labs and is currently under evaluation. Intel Xe-HPC is expected to make a debut with the manufacturer’s next-generation Xeon CPUs on Sapphire Rapids architecture.
Intel Xe-HPC (2-tile), Source: Raja Koduri